1. Field of the Invention
The present invention relates to a method of manufacturing a thin film transistor array substrate. More particularly, the present invention relates to a method of manufacturing a thin film transistor array substrate capable of preventing damage to a gate pad.
2. Description of the Related Art
Generally, a liquid crystal display device represents an image by adjusting a transmittance of a liquid crystal material using an electric field. For this purpose, the liquid crystal display device comprises a liquid crystal display panel in which liquid crystal cells are arranged in a matrix pattern, and a driving circuit for driving the liquid crystal display panel.
The liquid crystal display panel includes a thin film transistor array substrate and a color filter array substrate that face each other, a spacer for maintaining a cell gap between the two substrates and a liquid crystal material in the cell gap.
The thin film transistor array substrate includes gate lines and data lines, a thin film transistor formed as a switching device at each crossing of the gate lines and the data lines, a pixel electrode connected to the thin film transistor, and an alignment film applied on them. The gate lines and the data lines receive signals from the driving circuits through pads. The thin film transistor, in response to a scan signal supplied to a gate line, supplies a pixel voltage signal to the pixel electrode from the data line.
The color filter array substrate includes a color filter formed by a unit of the liquid crystal cell, a black matrix for reflecting external light and separating between the color filters, a common electrode commonly supplying a reference voltage to the liquid crystal cells, and the alignment film.
The liquid crystal display panel is fabricated by combining the thin film transistor array substrate and the color filter array substrate each of which are separately manufactured, injecting the liquid crystal material between the substrates and sealing the substrates with the liquid crystal material therebetween.
In such a liquid crystal display device, because the thin film transistor array substrate involves a semiconductor process and requires a plurality of mask processes, the manufacturing process is complicated and contributes to high costs in the manufacture of the liquid crystal display panel. In order to solve this, development has been done with respect to the thin film transistor array substrate to reduce the number of mask processes. This is because one mask process includes many sub-processes such as thin film deposition, cleaning, photolithography, etching, photo-resist stripping, inspection processes and the like. A four-round mask process has been developed in which one mask process is reduced from an existing five-round mask process that is employed as a standard mask process.
FIG. 1 is a plan view illustrating the thin film transistor array substrate using a four-round mask process, and FIG. 2 is a sectional view illustrating the thin film transistor array substrate taken along line I-I′ in FIG. 1.
The thin film transistor array substrate, shown in FIG. 1 and FIG. 2, includes gate lines 2 and data lines 4 crossing with each other and having a gate insulating film 44 therebetween on a lower substrate 42, a thin film transistor 6 formed at every crossing, and a pixel electrode 18 formed in the cell region resulting from the crossing pattern of the gate lines 2 and data lines 4. Further, the thin film transistor array substrate includes a storage capacitor 20 formed at an overlapped part of the pixel electrode 18 and a pre-stage gate line 2, a gate pad part 26 connected to the gate line 2 and a data pad part 34 connected to the data line 4.
The thin film transistor 6 includes a gate electrode 8 connected to the gate line 2, a source electrode 10 connected to the data line 4, a drain electrode 12 connected to a pixel electrode 18, and an active layer 14 of semiconductor pattern 47 defining a channel between the source electrode 10 and the drain electrode 12 and overlapping the gate electrode 8. The active layer 14 overlaps with a lower data pad electrode 36, a storage electrode 22, the data line 4, the source electrode 10 and the drain electrode 12, and further includes a channel portion defined between the source electrode 10 and the drain electrode 12. An ohmic contact layer 48 of the semiconductor pattern 47 for making an ohmic contact with the lower data pad electrode 36, the storage electrode 22, the data line 4, the source electrode 10 and the drain electrode 12 are further formed on the active layer 14. The thin film transistor 6 responds to a gate signal supplied to the gate line 2 and makes a pixel voltage signal supplied to the data line 4 charged to the pixel electrode 18.
The gate line 2 and the gate electrode 8 have a structure in which an aluminum system metal layer 2a of aluminum system metal, e.g., an aluminum neodium (AlNd) and a molybdenum (Mo) metal layer 2b of molybdenum (Mo) are stacked.
The pixel electrode 18 is connected to the drain electrode 12 of the thin film transistor 6 via a first contact hole 16 passing through a passivation film 50. The pixel electrode 18 generates a potential difference along with the common electrode formed on the upper substrate (not shown) by a pixel voltage charged. By this potential difference, the liquid crystal material located between the thin film transistor substrate and the upper substrate rotates due to a dielectric anisotropy, and makes incident light through the pixel electrode 18 from the light source (not shown) transmit to the upper substrate.
The storage capacitor 20 includes a pre-stage gate line 2, a storage electrode 22 overlapping the pre-stage gate line 2 having the gate insulating film 44, the active layer 14 and the ohmic contact layer 48 therebetween, and the pixel electrode 18 connected through a second contact hole 24 formed at the passivation film 50 and overlapped with the storage electrode 22 having the passivation film 50 therebetween. The storage capacitor 20 makes the pixel voltage charged to the pixel electrode 18 stably maintain until a next pixel voltage is charged.
The gate line 2 is connected to a gate driver (not shown) through the gate pad part 26. The gate pad part 26 includes a lower gate pad electrode 28 extending from the gate line 2 and an upper gate pad electrode 32 connected to the lower gate pad electrode 28 via a third contact hole 30 passing through both of the gate insulating film 44 and the passivation film 50. The lower gate pad electrode 28 has a structure in which an aluminum system metal layer 2a of the aluminum system metal and a molybdenum (Mo) metal layer 2b of the molybdenum (Mo) are stacked, which is similar to the structure of the gate line 2.
The data line 4 is connected to the data driver (not shown) through the data pad part 34. The data pad part 34 includes the lower data pad electrode 36 extending from the data line 4 and an upper data pad electrode 40 connected to the lower data pad electrode 36 via a fourth contact hole 38 passing through the passivation film 50.
A method of manufacturing the thin film transistor substrate having the above-mentioned configuration of FIGS. 1 and 2 will be described by way of a four-round mask process illustrated in FIGS. 3A to 3D.
In FIG. 3A, gate patterns are formed on the lower substrate 42.
On the lower substrate 42, an aluminum system metal, e.g, an aluminum neodium (AlNd), and a molybdenum (Mo) are sequentially stacked by a deposition method such as sputtering. Subsequently, the aluminum neodium (AlNd) and the molybdenum (Mo) are then patterned by photolithography using a first mask and an etching process to form the gate patterns including the gate line 2, the gate electrode 8 and the lower gate pad electrode 28, all of which have a double-layer structure of the aluminum metal layer 2a and the molybdenum (Mo) layer 2b. 
In FIG. 3B, the gate insulating film 44, the active layer 14, the ohmic contact layer 48 and source/drain patterns are sequentially formed on the lower substrate 42 provided with the gate patterns.
The gate insulating film 44, an amorphous silicon layer, a n+ amorphous silicon layer and a source/drain metal layer are sequentially formed on the lower substrate 42 having the gate patterns thereon by a deposition technique such as plasma enhanced chemical vapor deposition (PECVD) and sputtering.
A photo-resist pattern is formed on the source/drain metal layer by a photolithography process using a second mask. In this case, a diffractive exposure mask having a diffractive exposing part is used as a second mask wherein the diffractive exposing part corresponds to a channel portion of the thin film transistor. As a result, a photo-resist pattern of the channel portion has a lower height than a photo-resist pattern of the source/drain pattern part.
Subsequently, the source/drain metal layer is patterned by a wet etching process using the photo-resist pattern, to thereby form source/drain patterns including the data line 4, the source electrode 10, the drain electrode 12 being integral to the source electrode 10 and the storage electrode 22.
Next, the amorphous silicon layer and the n+ amorphous silicon layer are patterned at the same time by a dry etching process using the same photo-resist pattern to thereby form the semiconductor pattern 47 including the ohmic contact layer 48 and the active layer 14.
The photo-resist pattern having a relatively low height in the channel portion is removed by an ashing process. And then, the source/drain pattern and the ohmic contact layer 48 of the channel portion are etched by a dry etching process. Accordingly, the active layer 14 of the channel portion is exposed to separate the source electrode 10 from the drain electrode 12.
Thereafter, a remainder of the photo-resist pattern left on the source/drain pattern is removed using a stripping process.
The gate insulating film 44 is made of an inorganic insulating material such as silicon oxide (SiOx) or silicon nitride (SiNx). A metal of the source/drain pattern includes a molybdenum (Mo), a titanium (Ti), tantalum (Ta) or a molybdenum alloy.
In FIG. 3C, the passivation film 50 including first to fourth contact holes 16, 24, 30 and 38 is formed on the gate insulating film 44 having the source/drain patterns.
The passivation film 50 is entirely formed on the gate insulating film 44 having the source/drain patterns by a deposition technique such as a plasma enhanced chemical vapor deposition (PECVD). The passivation film 50 is patterned by photolithography using a third mask and an etching process to thereby form the first to fourth contact holes 16, 24, 30 and 38. The first contact hole 16 is formed in such a manner to pass through the passivation film 50 and expose the drain electrode 12, whereas the second contact hole 24 is formed in such a manner to pass through the passivation film 50 and expose the storage electrode 22. The third contact hole 30 is formed in such a manner to pass through the passivation film 50 and the gate insulating film 44 and expose the lower gate pad electrode 28, and the fourth contact hole 38 is formed in such a manner to pass through the passivation film 50 and expose the lower data pad electrode 36.
The passivation film 50 is made of an inorganic insulating material such as a material of the gate insulating film 44 or an organic insulating material having a small dielectric constant such as an acrylic organic compound, BCB (benzocyclobutane) or PFCB (perfluorocyclobutane).
In FIG. 3D, transparent electrode patterns are formed on the passivation film 50.
A transparent electrode material is entirely deposited on the passivation film 50 by a deposition technique such as a sputtering and the like. Then, the transparent electrode material is patterned by photolithography using a fourth mask and an etching process, to provide the transparent electrode patterns including the pixel electrode 18, the upper gate pad electrode 32 and the upper data pad electrode 40. The pixel electrode 18 is electrically connected, via the first contact hole 16, to the drain electrode 12 while being electrically connected, via the second contact hole 24, to the storage electrode 22 overlapping a pre-stage gate line 2. The upper gate pad electrode 32 is electrically connected, via the third contact hole 30, to the lower gate pad electrode 28. The upper data pad electrode 40 is electrically connected, via the fourth contact hole 38, to the lower data pad electrode 36. The transparent electrode pattern material may be made of an indium-tin-oxide (ITO), a tin-oxide (TO) or an indium-zinc-oxide (IZO).
Meanwhile, in the method of manufacturing the thin film transistor array substrate of the related art, upon forming the third contact hole 30 exposing the lower gate pad electrode 28, the aluminum system metal layer 2a is melted or rusted through the use of a developer or a stripper. As a result, damage occurs in the gate pad, which results in an unreliable electrical connection of the aluminum system metal layer 2a with the upper gate pad electrode 32.
More specifically describing with reference to FIGS. 4 and 5, the gate insulating film 44 and the passivation film 50 are stacked. Thereafter, a photo-resist pattern 55 is formed by a photolithography process and an etching process. Subsequently, the gate insulating film 44 and the passivation film 50 are patterned by using the photo-resist pattern 55 as a mask. At this time, when the gate insulating film 44 and the passivation film 50 are patterned, the molybdenum (Mo) layer 2b of the lower gate pad electrode 28 is also etched. As a result, the aluminum system metal layer 2a is exposed as shown in FIG. 4. After that, a stripping process is performed or a stripper is used to remove a poor photo-resist pattern and then to refresh the photo-resist pattern. Frequently the interface of the aluminum system metal layer 2a is corroded due to the stripping process or the stripper. Also, recently a developer including a lead ion (Pb+) is used in a stripping process, which causes damage to the aluminum system metal layer 2a. In other words, since an ionization tendency of aluminum Al is higher than that of lead Pb, the aluminum is easily ionized in an aqueous solution containing the lead and the aluminum. As a result, as shown in FIG. 5, the surface of the aluminum system metal layer 2a is damaged, or the aluminum system metal layer 2a is melted, which leads to damage to the pad.